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1 for more information www.linear.com/LT3840 typical a pplica t ion fea t ures descrip t ion wide input range synchronous regulator controller with accurate curr ent limit the lt ? 3840 is a high voltage synchronous step-down switching regulator controller capable of operating from a 2.5v to 60v supply. the LT3840s low quiescent current, when configured for user selectable burst mode operation, helps extend run time in battery-powered systems by increasing efficiency at light loads. the LT3840 uses a constant frequency, current mode architecture. high current applications are possible with large n-channel gate drivers capable of driving multiple low r ds(on) mosfets. an integrated buck-boost switching regulator generates a 7.5 v bias supply voltage for mosfet gate drive and ic power allowing higher efficiency operation over the entire input voltage range and eliminating the need for an external bias voltage. an accurate current limit set point regulates the maximum output current . a current monitor reports the average output current. high efficiency synchronous step-down converter 12v in to 3.3v out efficiency a pplica t ions l, lt , lt c , lt m , linear technology, burst mode, and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. n wide input range: 2.5v to 60v n integrated buck-boost supply for 7.5v mosfet gate drive n programmable constant-current operation with current monitor output n low i q : 75a, 12v in to 3.3v out n selectable low output ripple burst mode ? operation n v out up to 60v n adjustable and synchronizable: 50khz to 1mhz n internal ovlo protects for input transients up to 80v n accurate input overvoltage and undervoltage threshold n programmable soft-start with voltage tracking n power good and output ovp n 28-lead tssop and 38-lead 4 mm 6 mm qfn packages n automotive supplies n industrial systems n distributed dc power systems load current (a) 0 efficiency (%) 100 95 80 75 90 85 70 50 65 60 55 10 5 15 3840 ta01b 20 icomp ictrl imon auxsw2 auxsw1 auxbst LT3840 3840 ta01a intv cc boost tg sw bg sense + sense ? fb gnd v in v in 4v to 60v 68f 2 330f 2 49.9k 20k 7.68k 10k 16.9k 1500pf 2200pf 470pf 100pf 1f 1f 1.5h 2m 4.7f 33h en tk/ss auxvin uvlo ovlo pg sync mode rt v c v out 3.3v 20a 3840f lt 3840
2 for more information www.linear.com/LT3840 p in c on f igura t ion a bsolu t e maxi m u m r a t ings auxvin , v in , en and uvlo ....................... C0.3 v to 80 v pg .............................................................. C0.3 v to 25 v m ode ........................................................... C0.3 v to 9v sense + and sense C .................................. C0.3 v to 60 v se nse + to sense C ........................................... C1 v to 1v o vlo , v c , fb , sync , tk / ss and ictrl ....... C0.3 v to 6v (note 1) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 top view fe package 28-lead plastic tssop 28 27 26 25 24 23 22 21 20 19 18 17 16 15 auxsw1 pgnd auxvin sync rt tk/ss fb v c pg mode ovlo uvlo en v in auxbst auxsw2 intv cc bg bgrtn boost tg sw sense ? sense + icomp ictrl imon gnd 29 gnd ja = 30c/w, jc = 10c/w exposed pad (pin 29) is gnd, must be soldered to pcb 13 14 15 16 top view 39 gnd ufe package 38-lead (4mm 6mm) plastic qfn 17 18 19 38 37 36 35 34 33 32 24 25 26 27 28 29 30 31 8 7 6 5 4 3 2 1auxvin nc sync rt nc tk/ss fb v c pg nc mode ovlo nc intv cc bg bgrtn nc boost tg sw nc sense ? sense + icomp pgnd nc auxsw1 auxbst nc auxsw2 nc uvlo en v in nc gnd imon ictrl 23 22 21 20 9 10 11 12 ja = 38c/w, jc = 4c/w exposed pad (pin 39) is gnd, must be soldered to pcb o r d er i n f or m a t ion lead free finish tape and reel part marking* package description temperature range LT3840efe#pbf LT3840efe#trpbf LT3840fe 28-lead plastic tssop C40c to 125c LT3840ife#pbf LT3840ife#trpbf LT3840fe 28-lead plastic tssop C40c to 125c LT3840hfe#pbf LT3840hfe#trpbf LT3840fe 28-lead plastic tssop C40c to 150c LT3840mpfe#pbf LT3840mpfe#trpbf LT3840fe 28-lead plastic tssop C55c to 150c LT3840eufe#pbf LT3840eufe#trpbf 3840 38-lead (4mm 6mm) plastic qfn C40c to 125c LT3840iufe#pbf LT3840iufe#trpbf 3840 38-lead (4mm 6mm) plastic qfn C40c to 125c consult lt c marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. consult lt c marketing for information on nonstandard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ junction temperature range lt 3840 e ( no te 2) .............................. C40 c to 125 c lt 3840 i ............................................. C40 c to 125 c lt 3840 h ............................................ C40 c to 150 c lt 3840 mp ......................................... C55 c to 150 c lead temperature ( soldering , 10 sec ) tssop only .......................................................... 300 c s torage temperature ............................. C65 c to 150 c 3840f lt 3840
3 for more information www.linear.com/LT3840 e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. parameter conditions min typ max units input supply v in minimum operating voltage v in supply current v in burst mode current v in shutdown current v mode = 0v v en = 0.3v l l 20 20 0.1 2.5 30 1 v a a a auxv in minimum operating voltage auxv in overvoltage lockout auxv in supply current auxv in burst mode current auxv in shutdown current (note 3) v mode = 0v v en = 0.3v l l 60 300 0.1 0.1 2.5 1 v v a a a en enable threshold (rising) en hysteresis en pin bias current v en = 1.25v l 1.20 1.25 30 2 1.30 v mv na uvlo enable threshold (rising) uvlo hysteresis uvlo pin bias current v uvlo = 1.25v l 1.20 1.25 45 1 1.30 v mv na ovlo threshold (rising) ovlo hysteresis ovlo pin bias current v ovlo = 1.25v l 1.20 1.25 125 1 1.30 v mv na voltage regulation regulated fb voltage e- and i-grade l 1.237 1.250 1.263 v regulated fb voltage mp- and h-grade l 1.232 1.250 1.263 v fb overvoltage protection % above fb voltage l 8 12 16 % fb overvoltage protection hysteresis 2.5 % fb input bias current 5 20 na fb voltage line regulation 2.5v v in 60v 0.002 0.02 %/v fb error amp transconductance 300 s fb error amp sink/source current 25 a peak current limit sense voltage 0% duty cycle 80 95 110 mv peak current limit sense voltage 100% duty cycle 60 mv tk/ss charge current 9 a current regulation sense common mode range l 0 60 v average current limit sense voltage v ictrl = open v ictrl = 800mv l 47.5 50 40 52.5 mv mv imon voltage v sense = 50mv v sense = 20mv l 0.95 1.00 0.4 1.05 v v ictrl current v ictrl = 1v 7 a reverse protect sense voltage v mode = 7.5v C50 mv reverse current sense voltage offset v mode = v fb or v mode = 0v 5 mv sense input current sense + = sense C = 12v 300 a oscillator switching frequency r t = 49.9k r t = 348k r t = 13.7k l 280 300 50 1000 320 khz khz khz sync threshold 1.2 v 3840f lt 3840
4 for more information www.linear.com/LT3840 e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. parameter conditions min typ max units power good pg threshold as a percentage of v fb v fb rising l 87 90 93 % pg hysteresis as a percentage of v fb 5 % pg leakage v pg = 5v 0.1 1 a pg sink current v pg = 0.3v l 35 65 a mosfet gate drivers non-overlap time tg to bg 75 ns non-overlap time bg to tg 75 ns tg minimum on time 150 ns tg minimum off time v boost - v sw = 3v 240 ns tg maximum duty cycle r t = 49.9k 99 % tg, bg drive on voltage 7.5 v tg, bg drive off voltage 5 mv tg, bg drive rise time c tg = c bg = 3300pf 20 ns tg, bg drive fall time c tg = c bg = 3300pf 20 ns boost uvlo (rising) v boost - v sw 4.5 5.3 v boost uvlo hysteresis 350 mv internal auxiliary supply intv cc regulation voltage l 7.25 7.5 7.75 v intv cc uvlo threshold (rising) 6.25 6.5 6.75 v intv cc uvlo hysteresis 300 mv intv cc current in shutdown v en = 0.4v 6 a intv cc output current 2.5v v in 60v (note 4) l 100 ma intv cc burst mode current v mode = 0v 60 a note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the LT3840e is guaranteed to meet performance specifications from 0c to 125c junction temperature. specifications over the C40c to 125c operating junction temperature range are assured by design, characterization, and correlation with statistical process controls. the LT3840i is guaranteed over the C40c to 125c operating junction temperature range. the LT3840h is guaranteed over the full C40c to 150c operating junction temperature range. the LT3840mp is 100% tested and guaranteed over the C55c to 150c temperature range. high junction temperatures degrade operating lifetimes; operating lifetime is derated for junction temperatures greater than 125c. note 3: supply current specification does not include switch drive currents. actual supply currents will be higher. note 4: specification is not tested but is guaranteed by design, characterization and correlation with statistical process controls. 3840f lt 3840
5 for more information www.linear.com/LT3840 typical p er f or m ance c harac t eris t ics shutdown current vs temperature intv cc regulation voltage vs temperature i sense + + i sense C vs v sense(cm) switching frequency vs temperature en threshold voltage vs temperature uvlo threshold voltage vs temperature ovlo threshold vs temperature soft-start (tk/ss) current vs temperature temperature (c) ?50 intv cc regulation voltage (v) 7.7 7.5 7.4 7.6 7.3 7.0 7.2 7.1 50 0 100 125 3840 g05 150 25 ?25 75 temperature (c) ?50 en pin voltage (v) 1.40 1.35 1.30 1.20 1.15 1.25 1.10 90 1.05 1.00 95 50 0 100 125 3840 g01 150 25 ?25 75 en rising en falling temperature (c) ?50 uvlo pin voltage (v) 1.40 1.35 1.30 1.20 1.15 1.25 1.10 90 1.05 1.00 95 50 0 100 125 3840 g02 150 25 ?25 75 uvlo rising uvlo falling temperature (c) ?50 ovlo pin voltage (v) 1.30 1.25 1.15 1.05 1.00 1.20 1.10 0.95 0.90 50 0 100 125 3840 g03 150 25 ?25 75 ovlo rising ovlo falling t a = 25c, unless otherwise noted. common mode sense voltage (v) 0 sense + + sense ? bias current (a) 1600 1200 800 ?800 400 0 ?400 21 4 3840 g06 5 3 temperature (c) ?50 switching frequency (khz) 330 310 290 320 300 280 270 50 0 100 125 3840 g07 150 25 ?25 75 r t = 49.9k temperature (c) ?50 tk/ss current (a) 12 10 8 11 9 7 6 50 0 100 125 3840 g08 150 25 ?25 75 temperature (c) ?50 regulated feedback voltage (v) 1.28 1.26 1.24 1.27 1.25 1.23 1.22 50 0 100 125 3840 g09 150 25 ?25 75 regulated fb voltage vs temperature temperature (c) ?50 shutdown current (a) 20 18 14 10 8 16 12 6 0 4 2 50 0 100 125 3840 g04 150 25 ?25 75 v in auxv in 3840f lt 3840
6 for more information www.linear.com/LT3840 typical p er f or m ance c harac t eris t ics uvlo pin current vs uvlo voltage average current sense voltage vs temperature power good threshold vs temperature enable pin current vs enable voltage current monitor (imon) voltage vs temperature fb overvoltage threshold vs temperature t a = 25c, unless otherwise noted. enable pin voltage (v) 0 enable pin current (a) 1.6 1.2 0.8 1.4 1.0 0.6 0.4 0.2 0.0 30 50 3840 g10 60 2010 40 uvlo pin voltage (v) 0 uvlo pin current (na) 4 3 5 2 1 0 30 50 3840 g11 60 2010 40 temperature (c) ?50 average current sense voltage (mv) 55 50 40 30 45 35 25 10 20 15 50 0 100 125 3840 g12 150 25 ?25 75 ictrl = 500mv ictrl = float temperature (c) ?50 imon voltage (v) 1.1 1.0 0.8 0.6 0.9 0.7 0.5 0.2 0.4 0.3 50 0 100 125 3840 g13 150 25 ?25 75 v sense = 50mv v sense = 25mv temperature (c) ?50 power good threshold (v) 1.4 1.3 1.2 1.1 1.0 0.8 0.9 50 0 100 125 3840 g14 150 25 ?25 75 pg rising pg falling temperature (c) ?50 fb threshold (v) 1.6 1.5 1.4 1.3 1.2 1.0 1.1 50 0 100 125 3840 g15 150 25 ?25 75 fb falling fb rising 3840f lt 3840
7 for more information www.linear.com/LT3840 p in func t ions auxsw1 (pin 1/pin 36): auxsw1 is a switching node of the auxiliary bias supply. connect the pin to the auxiliary bias supply inductor. pgnd (pin 2/pin 38): pgnd is the high current ground return for the auxiliary bias supply. connect pgnd to the negative terminal of the intv cc decoupling capacitor and to system ground. auxvin (pin 3/pin 1): auxvin is the supply pin to the auxiliary bias supply. bypass the pin with a low esr ca - pacitor placed close to the pin and referenced to pgnd. sync (pin 4/ pin 3): sync allows the LT3840 switching frequency to be synchronized to an external clock. set the r t resistor such that the internal oscillator frequency is 15% below the minimum external clock frequency. if unused connect the sync pin to gnd. rt (pin 5/pin 4): an external resistor on rt sets the switching frequency of the synchronous controller and auxiliary bias supply. tk/ss (pin 6/pin 6): tk/ss is the LT3840 external tracking and soft-start input. the LT3840 regulates the v fb voltage to the smaller of the internal reference or the voltage on the tk/ss pin. an internal pull-up current source is connected to this pin. a capacitor (c ss ) to ground sets the ramp rate. alternatively, a resistor divider on another voltage supply connected to this pin allows the LT3840 output to track another supply during start-up. leave the pin open if the tracking and soft-start functions are unused. fb (pin 7/pin 7): the regulator output voltage is set with a resistor divider connected to fb. fb is also the input for the output overvoltage and power good comparators. v c ( pin 8/pin 8): v c is the compensation node for the output voltage regulation control loop. pg (pin 9/pin 9): pg is a power good pin and is the open- drain output of an internal comparator. mode (pin 10/pin 11): mode is used to enable or disable burst mode operation. connect mode to ground for burst mode operation. connect the pin to fb for pulse-skipping mode. connect mode to intv cc for continuous mode. ovlo (pin 11/pin 12): ovlo has a precision threshold with hysteresis to implement an accurate overvoltage lockout ( ovlo). controller switching is disabled during an overvoltage lockout ( ovlo) event. intv cc regulation is maintained during an ovlo event. connect the pin to gnd to disable the function. uvlo (pin 12/pin 13): uvlo has a precision threshold with hysteresis to implement an accurate undervoltage lockout ( uvlo). uvlo enables the controller switching. connect the pin to v in to disable the function. en (pin 13/pin 14): en has a precision ic enable threshold with hysteresis. en enables the auxiliary bias supply and controller switching. connect the pin to v in to disable the function. en also has a lower threshold to put the LT3840 into a low current shutdown mode where all internal cir - cuitry is disabled. v in (pin 14/pin 15): v in provides an internal dc bias rail and should be decoupled to gnd with a low value (0.1f), low esr capacitor located close to the pin. gnd (pin 15, exposed pad pin 29/pin 17, exposed pad pin 39): ground. solder gnd and the exposed pad directly to the pcb ground plane. imon (pin 16/pin 18): the voltage on imon represents the average output current of the converter. a small value capacitor filters the ripple voltage associated with the inductor ripple current. ictrl (pin 17/pin 19): the maximum average output current is programmed with a voltage applied to ictrl. if unused, leave floating. icomp ( pin 18/pin 20): a capacitor and resistor connected to icomp compensates the average current limit circuit. sense + (pin 19/pin 21): sense + is the positive input for the differential current sense comparator. sense C (pin 20/pin 22): sense C is the negative input for the differential current sense comparator. sw (pin 21/pin 24): sw is the high current return path of the tg mosfet driver and is externally connected to the negative terminal of the boost capacitor. (tssop/qfn) 3840f lt 3840
8 for more information www.linear.com/LT3840 p in func t ions (tssop/qfn) tg (pin 22/pin 25): tg is the high current gate drive for the top n-channel mosfet. boost (pin 23/pin 26): boost is the supply for the bootstrapped tg gate drive and is externally connected to a low esr ceramic capacitor referenced to sw. bgrtn ( pin 24/pin 28): bgrtn is the high current return path of the bg mosfet driver and is externally connected to the negative terminal of the intv cc capacitor. bg (pin 25/pin 29): bg is the high current gate drive for the bottom n-channel mosfet. intv cc ( pin 26/pin 30): intv cc is the auxiliary bias supply output. bypass the pin with a low esr capacitor placed close to the pin. intv cc provides supply for LT3840 internal bias and mosfet gate drivers. the intv cc pin cannot be back driven with a separate supply. auxsw2 (pin 27/pin 33): auxsw2 is a switching node of the auxiliary supply and is connected to the auxiliary bias supply inductor. auxbst (pin 28/pin 35): auxbst provides drive voltage for the auxiliary supply and is connected to a low esr capacitor referenced to auxsw1. 3840f lt 3840
9 for more information www.linear.com/LT3840 o pera t ion o verview the LT3840 provides a solution for a high efficiency, general purpose dc/dc converter. it is a wide input voltage range switching regulator controller ic that uses a program - mable fixed frequency, peak current mode architecture. an internal switching regulator efficiently provides an auxiliary bias supply to drive multiple, large n-channel mosfet switches. the LT3840 includes functions such as average output current control and monitoring, micro-power operation with low output ripple, soft-start, output voltage tracking, power good and a handful of protection features. voltage control loop the LT3840 uses peak current mode control to regulate the supply output voltage. the error amplifier ( ea) gener - ates an error voltage (v c ) based on the difference between the feedback ( fb) voltage and an internal reference . the externally co m pensated v c voltage generates a threshold for the differential current sense comparator. during normal operation, the LT3840 internal oscillator runs at the programmed frequency. at the beginning of each oscillator cycle, the tg switch drive is turned on. the tg switch drive stays enabled until the sensed inductor current exceeds the v c derived threshold of the current sense comparator. if the current comparator threshold is not reached for the entire oscillator cycle, the switch driver stays on for up to eight cycles. if after eight cycles the tg switch driver is still on, it is turned off to regenerate the boost boot - strapped supply. when the load current increases, the fb voltage decreases relative to the reference causing the ea to increase the v c voltage until the average inductor current matches the new load current. refer to figure 1 for a block diagram of the LT3840 voltage control loop. figure 1. peak current mode voltage control functional block diagram intv cc boost v in external components v out intv cc sw tg driver driver anti shoot thru bg bgrtn sense + sense ? v ref 3840 bd fb sync rt r sq oscillator ? + v c ? + ea 3840f lt 3840
10 for more information www.linear.com/LT3840 light load operation (burst mode operation, pulse-skipping mode or continuous mode) the LT3840 is capable of operating in burst mode, pulse- skipping mode, or continuous mode. connect the mode pin to gnd for burst mode operation, to the fb pin for pulse-skipping mode, or to intv cc for continuous mode. in burst mode operation the LT3840 forces a minimum peak inductor current via an internal clamp on the v c pin. if the average inductor current is greater than the load current the output voltage will begin to increase and the error amplifier, ea, will attempt to decrease the v c volt- age. when the internal voltage clamp on v c is engaged and the fb voltage increases slightly, the LT3840 goes into sleep mode. in sleep mode, both external mosfets are turned off and much of the internal circuitry is turned off, reducing the quiescent current. the load current is supplied by the output capacitor. as the output voltage decreases, the LT3840 comes out of sleep mode and the controller resumes normal operation by turning on the tg mosfet on the next cycle of the internal oscillator. the output voltage increases and the controller goes back to sleep. this cycle repeats until the average load current is greater than the minimum forced peak inductor current. when burst mode operation is selected, the inductor current is not allowed to go negative. a reverse current comparator turns off the bg mosfet just before the inductor current reaches zero, preventing it from revers - ing and going negative. thus, the controller operates in discontinuous operation. in pulse-skipping mode, during light loads, the supply operates in discontinuous mode where the inductor cur - rent is not allowed to reverse direction. output voltage regulation is maintained by skipping tg on pulses. at light loads pulse-skipping mode is more efficient than forced continuous mode, but not as efficient as burst mode operation. in continuous operation the inductor current is allowed to reverse direction at light loads or under large transient conditions. the reverse current comparator protects the bg mosfet by turning it off if the reverse current exceeds the maximum reverse current sense threshold voltage. constant current operation for applications requiring a regulated current source the LT3840 has a control loop to accurately regulate the aver - age output current. a current monitor function provides output current information for telemetry and diagnostics. the current through the sense resistor, r sense , produces a voltage applied to the sense pins. the differential sense voltage is amplified by 20 x, buffered and output to the imon pin. the capacitor on the imon pin filters the ripple component to average the signal. the 20 x amplified differential sense voltage is also applied to an internal gm amplifier and compared against either 1v or ictrl voltage, whichever is smaller. a voltage applied to ictrl reduces the maximum average current sense threshold. when the 20 amplified differential sense voltage exceeds the 1 v internal reference or the ictrl voltage the icomp node is driven high and v c is pulled o pera t ion 3840f lt 3840
11 for more information www.linear.com/LT3840 o pera t ion low. the v c voltage is the dc control node that sets the peak inductor current. a resistor and capacitor on icomp compensate the current control loop. figure 2 includes the block diagram of the average current control loop and transfer functions showing the relationship between v sense , ictrl and imon. auxiliary bias supply the LT3840 wide input voltage range is made possible with the auxiliary bias supply switching regulator. other switching regulator controllers typically use a linear volt - age regulator to provide the gate drive voltage from v in . this approach is limited by power dissipation at high input voltage and dropout at low voltage. the LT3840 bias regulator efficiently generates a 7.5 v bias voltage, capable of adequately driving large multiple mosfets, at input voltages as low as 2.5v and as high as 60v. the auxiliary bias supply is a monolithic buck-boost, peak current mode topology. the switching frequency is fixed and synchronized with the LT3840 synchronous buck con - troller. the switching regulator is internally compensated figure 2. average output current limit functional block diagram and transfer curves sense + sw r sense v out c out sense ? ? + 1v ? ? + gm 20x icomp maximum average current control ictrl imon v c v ictrl (mv) transfer function max. avg. sense voltage vs ictrl 300200100 0 30 40 50 600 800 20 400 500 700 900 1000 10 0 v sense (mv) transfer function imon vs avg. sense voltage 1000 900 800 700 600 500 400 300 200 100 0 v imon (mv) v sense (mv) 40 50 0 10 20 30 3840 f02 ? + 3840f lt 3840
12 for more information www.linear.com/LT3840 o pera t ion and current limited. figure 3 is a functional block diagram of the auxiliary bias supply. auxiliary bias supply start-up and shutdown the LT3840 auxiliary bias supply is enabled with the en - able ( en) pin. when the en pin voltage exceeds a diode threshold the LT3840 comes out of the low quiescent cur- rent shutdown mode and turns on the internal reference (v ref ) and internal bias (v reg ). when the en pin voltage exceeds its precision voltage threshold the auxiliary bias switching regulator is activated and the intv cc voltage is regulated. figure 4 is a functional block diagram of the auxiliary bias supply start-up. the auxiliary bias supply has its own enable pin to allow the intv cc to be activated independent of the controller. intv cc may be used to drive other circuitry in the applica- tion such as an ldo. figure 3. auxiliary bias supply functional block diagram figure 4. auxiliary bias supply start-up functional block diagram 3840 f04 internal reference oscillator linear regulator ? + ? + en v ref v ref v in auxvin intv cc auxiliary bias supply v reg 3840 f03 ? + ? + v in > 18v auxbst c auxbst lpwr intv cc external components auxsw1 auxsw2 internal compensation r s q auxvin v ref c intvcc 3840f lt 3840
13 for more information www.linear.com/LT3840 o pera t ion soft-start/output voltage tracking the soft-start function controls the slew rate of the power supply output voltage during start-up. a controlled output voltage ramp minimizes output voltage overshoot, reduces inrush current from the v in supply, and facilitates supply sequencing. tk/ ss is an additional input to the error ampli - fier ( ea). the voltage control loop regulates the out- put via the fb pin to whichever pin is lower, v ref or tk/ss. an internal current source and a capacitor on the pin program the output voltage ramp time. drive the pin with a voltage to use the output voltage tracking function for supply sequencing. the tk/ss voltage is clamped to a diode above the fb volt - age, therefore , during a short-circuit the tk/ss voltage is pulled low because the fb voltage is low. once the short has been removed the fb voltage starts to recover. the soft- start circuit takes control of the output voltage slew rate once the fb voltage has exceeded the slowly ramping tk/ ss voltage, reducing the output voltage overshoot through a short-circuit recovery. during a fault condition such as uvlo, ovlo or overtemperature, the soft-start capacitor is discharged. if unused, the pin can be left open and the internal current source will pull the pin voltage above the soft-start operating range. figure 5 is a functional block diagram of the LT3840 soft-start/tracking function. power good and output overvoltage protection when fb is within range of its regulated value an internal n-channel mosfet, on the pg pin, is turned off allowing an external resistor to pull pg high. power good is valid when the LT3840 is enabled with the en pin and the v in voltage is above 2.5v. the LT3840 output overvoltage protection feature disables the synchronous buck controller switching when the fb pin exceeds its regulated value by a given amount ( see electrical specification table). when this event occurs the pg pin voltage is pulled low. input overvoltage lockout the LT3840 is capable of withstanding input voltage transients up to 80 v. when the voltage on the auxvin pin exceeds 60 v the auxiliary bias switching regulator is disabled. figure 5. soft-start and output voltage tracking functional block diagram and transfer curve i soft-start fault v ref v out ? + + fb tk/ss v c ea transfer function fb vs tk/ss 0.1 0.2 0.4 0.3 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 fb(v) tk/ss (v) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 3840 f05 3840f lt 3840
14 for more information www.linear.com/LT3840 switching frequency the choice of switching frequency is a trade-off between converter efficiency and component size. low frequency operation improves efficiency by reducing mosfet switching losses and gate charge losses. however, lower frequency operation requires more inductance for a given amount of ripple current, resulting in larger inductor size. increasing the ripple current requires additional output capacitance to maintain the same output ripple voltage. for converters with extremely high or low step-down v in to v out ratios, another consideration is the minimum on and off times of the LT3840. a final consideration for operating frequency is in noise-sensitive systems where it is often desirable to keep the switching noise out of a sensitive frequency band. the LT3840 uses a constant frequency architecture pro - grammable with a single resistor ( r t ) over a 50 khz to 1 mhz range. the value of r t for a given operating frequency can be chosen from table 1 or from the following equation: r t (k) = 2.32 ? 10 4 ? f sw (C1.08) table 1. recommended 1% standard values r t (k) f sw (khz) 348 50 158 100 76.8 200 49.9 300 36.5 400 28.0 500 23.2 600 19.1 700 16.5 800 14.3 900 13.7 1000 a pplica t ions i n f or m a t ion inductor selection the critical parameters for the selection of an inductor are minimum inductance value, saturation current and rms current. for a given i l , the inductance value is calculated as follows: l v out ? v in(max) C v out f sw ? v in(max) ? i l the typical range of values for i l is (0.2 ? i out(max) ) to (0.5 ? i out(max) ), where i out(max) is the maximum load current of the supply. using i l = 0.3 ? i out(max) yields a good design compromise between inductor performance versus inductor size and cost. a value of i l = 0.3 ? i out( max) produces a 15% of i out( max) ripple current around the dc output current of the supply. lower values of i l require larger and more costly magnetics. higher values of i l will increase the peak currents, requiring more filtering on the input and output of the supply. if i l is too high, the slope compensation circuit is ineffective and current mode instability may occur at duty cycles greater than 50%. to satisfy slope compensation requirements the minimum inductance is calculated as follows: l min > v out ? 2dc max C 1 dc max ? r sense ? 30 f sw magnetics vendors specify the saturation current, the rms current or both. when selecting an inductor based on inductor saturation current, use the peak current through the inductor, i out(max) + i l /2. the inductor saturation current specification is the current at which the inductance, measured at zero current, decreases by a specified amount, typically 30%. when selecting an inductor based on rms current rating, use the average current through the inductor, i out( max) . the rms current specification is the rms current at which the part has a specific temperature rise, typically 40c, above 25 c ambient. after calculating the minimum inductance value, the saturation current and the rms current for your design, select an off-the-shelf inductor. contact the applications group at linear technology for further support. for more detailed information on selecting an inductor, please see the inductor selection section of linear technology application note 44. 3840f lt 3840
15 for more information www.linear.com/LT3840 a pplica t ions i n f or m a t ion mosfet selection tw o external n- channel mosfets are used with the LT3840 controller, one top ( main) switch, and one bot - tom ( synchronous) switch. the gate drive levels are set by the intv cc voltage. therefore, standard or logic level threshold mosfets can be used. selection criteria for the power mosfets include break - down voltage (bv dss ), maximum current (i outmax ), on- resistance (rds on ) and gate charge. first select a mosfet with a bv dss greater than v in . next consider the package and current rating of the device. the maximum current rating of the device typically corresponds to a particular package. the rms current of each device is calculated below: top switch duty cycle (dc top ) = v out v in top switch rms current = dc top ? i outmax bottom switch duty cycle (dc bot ) = v in C v out v in bottom switch rms current = dc bot ? i outmax select a device that has a continuous current rating greater than the calculated rms current. lastly, consider the rds on and gate charge of the mosfet. these two parameters are considered together because they are typically inversely proportional to one another. the rds on determines the conduction losses of the mosfet and the gate charge determines the switching losses. the switching and conduction losses of each mosfet can be calculated as follows: p cond(top) =i out(max) 2 ? v out v in ? r ds(on) p cond(bot) =i out(max) 2 ? v in C v out v in ? r ds(on) note that rds on has a large positive temperature depen- dence. the mosfet manufacturers data sheet contains a cur ve, rds on vs temperature. in the main mosfet, transition losses are proportional to v in 2 and can be con- siderably large in high voltage applications (v in > 20v). calculate the maximum transition losses: p tran(top) = v in ? i out ? f sw ? q gsw i drive where q gsw can be found in the mosfet specification or calculated by: q gsw = q gd + q gs 2 and i drive = 1a the total maximum power dissipations of the mosfet are: p top(total) = p cond(top) + p tran(top) p bot(total) = p cond(bot) complete a thermal analysis to ensure that the mosfets junction temperatures are not exceeded. t j = t a + p (total) ? ja where ja is the package thermal resistance and t a is the ambient temperature. keep the calculated t j below the maximum specified junction temperature, typically 150 c. note that when v in is high and f sw is high, the transition losses may dominate. a mosfet with higher rds on and lower gate charge may provide higher efficiency. mosfets with a higher voltage bv dss specification usually have higher rds on and lower gate charge. a schottky diode can be inserted in parallel with the synchronous mosfet to conduct during the dead time between the conduction of the two power mosfets. this prevents the body diode of the bottom mosfet from turn - ing on , storing charge during the dead time and requiring a reverse recovery period. input capacitor selection a local input bypass capacitor is required for buck convert - ers because the input current is pulsed with fast rise and fall times. the input capacitor selection criteria are based on 3840f lt 3840
16 for more information www.linear.com/LT3840 the bulk capacitance and rms current capability. the bulk capacitance will determine the supply input ripple voltage. the rms current capability is used to prevent overheating the capacitor. the bulk capacitance is calculated based on maximum input ripple, v in : c in(bulk) = i out(max) ? v out v in ? f sw ? v in(min) v in is typically chosen at a level acceptable to the user. a good starting point is 100 mv to 200 mv. aluminum electrolytic capacitors are a good choice for high voltage, bulk capacitance due to their high capacitance per unit area. the capacitors rms current is: i cin(rms) =i out v out (v in C v out ) (v in ) 2 if applicable, calculate it at the worst-case condition, v in = 2v out . the rms current rating of the capacitor is specified by the manufacturer and should exceed the calculated i cin(rms) . due to their low esr (equivalent series resistance), ceramic capacitors are a good choice for high voltage, high rms current handling. note that the ripple current ratings from aluminum electrolytic capacitor manufacturers are based on 2000 hours of life. this makes it advisable to further derate the capacitor or to choose a capacitor rated at a higher temperature than required. the combination of aluminum electrolytic capacitors and ceramic capacitors is an economical approach to meeting the input capacitor requirements. the capacitor voltage rating must be rated greater than maximum v in voltage. multiple capacitors may also be paralleled to meet size or height requirements in the design. locate the capaci - tor very close to the mosfet switch and use short, wide pcb traces to minimize parasitic inductance. use a small (0.1f to 1 f) bypass capacitor between the chip v in pin and gnd, placed close to the LT3840. output capacitor selection the output capacitance, c out , selection is based on the designs output voltage ripple , v out and transient load requirements. v out is a function of i l and the c out esr. it is calculated by: ? v out = ?i l ? esr+ 1 8 ? f sw ? c out ( ) ? ? ? ? the maximum esr required to meet a v out design requirement can be calculated by: esr(max)= ?v out ( ) l ( ) f sw ( ) v out ? 1? v out v in(max) ? ? ? ? ? ? worst-case v out occurs at the highest input voltage. use paralleled multiple capacitors to meet the esr require- ments. increasing the inductance is an option to lower the esr requirements. for extremely low v out , an additional lc filter stage can be added to the output of the supply. linear technologys application note 44 has some good tips on sizing an additional output filter. output voltage programming a resistive divider sets the dc output voltage according to the following formula: r2 =r1 v out 1.250v ? 1 ? ? ? ? the external resistor divider is connected to the output of the converter as shown in figure 6. a pplica t ions i n f or m a t ion figure 6. output voltage feedback divider 3840 f06 fb r2 c out v out l1 r1 tolerance of the feedback resistors will add additional er- ror to the output voltage. the v fb pin input bias current is typically 5 na, so use of extremely high value feedback resistors results in a converter output that is slightly 3840f lt 3840
17 for more information www.linear.com/LT3840 higher than expected. bias current error at the output can be estimated as: dv out(bias) = 5na ? r2 great care should be taken to route the v fb line away from noise sources, such as the inductor or the sw node. output current programming and monitoring the average current control loop of the LT3840 accurately regulates the maximum output current of the switching regulator. the default maximum differential sense volt - age, v sense(max) , is 50 mv, but a voltage applied to the ictrl pin will program it lower. a 0 v to 1 v range on the ictrl pin corresponds to 0 mv to 50 mv differential sense voltage. a way to provide the ictrl programming voltage is to connect a linear regulator or voltage divider to the intv cc pin. once the maximum differential sense voltage is determined the r sense current sense resistor is calculated as follows: r sense = v sense(max) i out(max) select a current sense resistor where the maximum power dissipation rating is greater than the calculated power dissipation: p d(rsense) = r sense ? i out(max) 2 the average current control loop is compensated at the icomp pin with a resistor and capacitor connected to gnd. the imon pin is an accurate output current monitor pin. the LT3840 outputs a voltage that is 20 times the differential sense voltage. a 0 mv to 50 mv differential sense voltage corresponds to a 0 v to 1 v imon voltage. a capacitor on the pin filters the voltage ripple due to the inductor ripple current. typical capacitor values on the pin range from 1000pf to 0.1 f. the larger the capacitor value, the lower the ripple. the capacitor does not affect the average cur - rent control loop. output short-circuit current foldback the LT3840 defaults to a straight line current limit where the short-circuit current is the same as the drop out cur- rent. for applications that require current foldback in a a pplica t ions i n f or m a t ion figure 7. output short-circuit foldback current circuit 3840 f07 ictrl r1 v out d1 short- circuit load condition , a diode and resistor connected from v out to the ictrl pin is recommended ( see figure 7). the foldback current in short- circuit, i out(sc) , is calculated as follows: i out(sc) = (v f(d1) + 7a ? r1) 20 ? r sense where v f is the forward voltage on the diode d1 at ~7ua current. internal power supply the internal auxiliary supply requires three external com - ponents (c intvcc , c auxbst and l pwr ) for operation, as shown in figure 3. c intvcc , a 4.7f /10 v ceramic capacitor, bypasses intv cc . c auxbst , a 1 f/10v ceramic capacitor, connected between the auxbst pin and the auxsw1 pin, provides bootstrapped drive to the internal switch. a 33 h inductor with a saturation current greater than 0.6a is recommended for most applications. the coilcraft me3220-333 is a good fit. c boost capacitor selection the recommended value of the boost capacitor, c boost , is at least 100 times greater than the total gate capacitance of the topside mosfet. typical values for most applica - tions range from 0.1f to 1f. soft-start and voltage tracking the desired soft-start time (t ss ) is programmed via the c ss capacitor as follows: c ss = t ss ? 9a 1.75 3840f lt 3840
18 for more information www.linear.com/LT3840 the soft-start capacitor is reset under fault conditions including uvlo, en, ovlo, overtemperature shutdown and intv cc uvlo. the soft-start pin is clamped through a diode to the v fb pin. therefore, the soft-start pin is reset during a short- circuit minimizing overshoot upon recovery . en, uvlo and ovlo en has a precision voltage threshold with hysteresis to enable the LT3840 auxiliary bias supply and synchronous controller. the pin is typically connected to v in through a resistor divider, however, it can be directly connected to v in . a lower voltage threshold on the en pin is used to put the LT3840 into a low quiescent current shutdown mode. uvlo has a precision voltage threshold with hysteresis to enable the LT3840 synchronous controller. the pin is typically connected to v in through a resistor divider, however, it can be directly connected to v in . ovlo has a precision voltage threshold with hysteresis to disable the LT3840 synchronous controller. the pin is typically connected to v in through a resistor divider. ovlo can be directly connected to gnd to disable the function. switching frequency synchronization the oscillator can be synchronized to an external clock. set the r t resistor 15% below the lowest synchronized frequency. the rising edge of the sync pin waveform triggers the discharge of the internal oscillator capacitor. if unused, connect the sync pin to gnd. layout considerations checklist the following is a list of recommended layout consider - ations: ? locate the v in , auxvin, intv cc , auxbst and boost pin bypass capacitors in close proximity to the LT3840. ? create a solid gnd plane, preferably on layer two of the pcb. ? minimize the hot loop. (see figure 9) ? use short wide traces for the mosfet gate drivers (tg and bg), as well as, gate drive supply and return ( intv cc and boost, bgrtn and sw). ? connect the fb pin directly to the feedback resistors, independent of any other nodes (i.e. sense + ). ? locate the feedback resistors in close proximity to the LT3840 fb pin. ? route the sense C and sense + traces close together and keep as short as possible. ? solder the LT3840 exposed pad to the pcb. add multiple vias to connect the exposed pad to the gnd plane. ? per the manufacturers specification, add a sufficient pcb pad around mosfets and inductor to dissipate heat. a pplica t ions i n f or m a t ion figure 8. precision en, uvlo and ovlo resistor divider 3840 f08 en, uvlo or ovlo pin r a v in r b figure 9. hot loop layout for synchronous buck regulator 3840 f09 hot loop bg tg sw c in v in resistors are chosen by first selecting r b . then calculate r a with the following formula: r a = r b ? v threshold 1.25v ? 1 ? ? ? ? v threshold is the v in referred voltage at which the supply is enabled (uvlo and en) or disabled (ovlo). 3840f lt 3840
19 for more information www.linear.com/LT3840 typical a pplica t ions wide input range, high power output, 15v to 60v input to 12v, 20a output icomp ictrl imon auxsw2 auxsw1 auxbst LT3840 3840 ta02 intv cc boost tg sw bg sense + sense ? fb gnd v in v in 15v to 60v en tk/ss 0.01f 100pf auxvin uvlo ovlo pg intv cc 174k 887k 1f 4.7f 1n4448 1f m1 2 m2 2 d1 l1, 5.6h r sense 2.5m m1: infineon, bsc160n10ns3 m2: infineon, bsc070n1ons3 l1: vishay, ihlp6767gzer5r6ma1 l2: coilcraft, me3220-333kl c in : suncon 100ce68fs c out1 : sanyo, 16svpf560m c out2 : taiyo yuden, emk325bj226mm-t d1: diodes inc. pds5100h c out1 560f l2, 33h c in 68f 2 60.4k 20k 10k 86.6k 20k 7.68k 470pf 100pf sync mode rt v c 49.9k 2200pf 2200pf c out2 22f 4 v out 12v 20a 3840f lt 3840
20 for more information www.linear.com/LT3840 typical a pplica t ions low part count application, 6v to 60v input to 5v, 10a output icomp ictrl imon auxsw2 auxsw1 auxbst LT3840 3840 ta03 intv cc boost tg sw bg sense + sense ? fb gnd v in v in 6v to 60v en 470pf auxvin uvlo ovlo pg 1f 4.7f 1n4448 1f m1 m2 l1, 5.6h r sense 5m m1: infineon, bsc160n10ns3 m2: infineon, bsc070n1ons3 l1: vishay, ihlp5050 l2: coilcraft, me3220-333kl c in : suncon 100ce68fs c out : sanyo, 16svpc270m l2, 33h c in 68f 2 100k 301k 20k sync mode rt v c tk/ss 49.9k 2200pf c out 270f v out 5v 10a 3840f lt 3840
21 for more information www.linear.com/LT3840 typical a pplica t ions low voltage, high current output, 4v to 60v input to 3.3v, 20a icomp ictrl imon auxsw2 auxsw1 auxbst LT3840 3840 ta04 intv cc boost tg sw bg sense + sense ? gnd fb v in v in 4v to 60v en tk/ss 0.01f 100pf auxvin uvlo ovlo pg intv cc 174k 887k 1f 4.7f 1n4448 1f m1 2 m2 2 d1 l1, 1.7h m1: infineon, bsc160n10ns3 m2: infineon, bsc070n1ons3 l1: wrth, 7443556130 l2: coilcraft, me3220-333kl c in : suncon 100ce68fs c out1 : sanyo, 16svpf560m c out2 : taiyo yuden, emk325bj226mm-t d1: diodes inc. pds5100h l2, 33h c in 68f 2 60.4k 20k 10k 16.9k 20k 7.68k 470pf sync mode rt v c r sense 2.5m 49.9k 2200f 2200f c out2 22f 4 v out 3.3v 20a c out1 560f 3840f lt 3840
22 for more information www.linear.com/LT3840 p ackage descrip t ion please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. fe28 (ea) tssop rev j 1012 0.09 ? 0.20 (.0035 ? .0079) 0 ? 8 0.25 ref 0.50 ? 0.75 (.020 ? .030) 4.30 ? 4.50* (.169 ? .177) 1 3 4 5 6 7 8 9 10 11 12 13 14 192022 21 151618 17 9.60 ? 9.80* (.378 ? .386) 7.56 (.298) 3.05 (.120) 28 2726 25 24 23 1.20 (.047) max 0.05 ? 0.15 (.002 ? .006) 0.65 (.0256) bsc 0.195 ? 0.30 (.0077 ? .0118) typ 2 recommended solder pad layout exposed pad heat sink on bottom of package 0.45 0.05 0.65 bsc 4.50 0.10 6.60 0.10 1.05 0.10 7.56 (.298) 3.05 (.120) millimeters (inches) *dimensions do not include mold flash. mold flash shall not exceed 0.150mm (.006") per side note: 1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale see note 4 4. recommended minimum pcb metal size for exposed pad attachment 6.40 (.252) bsc fe package 28-lead plastic tssop (4.4mm) (reference ltc dwg # 05-08-1663 rev j) exposed pad variation ea 3840f lt 3840
23 for more information www.linear.com/LT3840 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. p ackage descrip t ion please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. 4.00 0.10 2.40 ref 6.00 0.10 note: 1. drawing is not a jedec package outline 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 0.10 3837 1 2 bottom view?exposed pad 4.40 ref 0.75 0.05 r = 0.115 typ r = 0.10 typ pin 1 notch r = 0.30 or 0.35 45 chamfer 0.20 0.05 0.40 bsc 0.200 ref 0.00 ? 0.05 (ufe38) qfn 0708 rev b recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.70 0.05 0.20 0.05 0.40 bsc 2.40 ref 4.40 ref 5.10 0.05 6.50 0.05 2.65 0.05 3.10 0.05 4.50 0.05 package outline 2.65 0.10 4.65 0.10 4.65 0.05 ufe package 38-lead plastic qfn (4mm 6mm) (reference ltc dwg # 05-08-1750 rev b) 3840f lt 3840
24 for more information www.linear.com/LT3840 ? linear technology corporation 2014 lt 0214 ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/LT3840 r ela t e d p ar t s typical a pplica t ion part number description comments lt3845a 60v, low i q , single output synchronous step-down dc/dc controller synchronizable fixed frequency 100khz to 600khz, 4v v in 60v, 1.23v v out 36v, i q = 120a, tssop-16 package lt3844 60v, low i q , single output step-down dc/dc controller synchronizable fixed frequency 50khz to 600khz, 4v v in 60v, 1.23v v out 36v, i q = 120a, tssop-16 package ltc3864 60v, low i q , step-down dc/dc controller 100% duty cycle capability selectable fixed frequency 200khz to 600khz, 3.5v v in 60v, 0.8v v out v in , i q = 40a, msop-10e package ltc3891 60v, low i q , synchronous step-down dc/dc controller phase-lockable fixed frequency 50khz to 900khz, 4v v in 60v, 0.8v v out 24v, i q = 50a ltc3890/ ltc3890-1/ ltc3890-2 60v, low i q , dual 2-phase synchronous step-down dc/dc controller phase-lockable fixed frequency 50khz to 900khz, 4v v in 60v, 0.8v v out 24v, i q = 50a ltc3859a low i q , triple output buck/buck/boost synchronous dc/dc controller all outputs remain in regulation through cold crank, 2.5v v in 38v, v out(bucks) up to 24v, v out(boost) up to 60v, i q = 27a lt8705 30v v in and v out synchronous 4-switch buck-boost controller synchronizable fixed frequency 100khz to 400khz, 2.8v v in 80v, 1.3v v out 30v, four regulation loops inverting application, 24v input to C15v, 10a icomp ictrl imon auxsw2 auxsw1 auxbst LT3840 3840 ta05 intv cc boost tg sw bg sense + sense ? gnd fb v in v in 18v to 36v en tk/ss 33nf 100pf auxvin uvlo ovlo pg 1m 1f 4.7f 1n4448 1f m1 m2 d1 l1, 15h m1: infineon, bsc160n10ns3 m2: infineon, bsc070n1ons3 l1: wrth, 7443631500 l2: coilcraft, me3220-333kl d1: diodes inc. pds5100h l2, 33h c in 68f 2 80.6k 10k 110k 39.2k 7.68k 470pf sync mode rt v c r sense 5m 49.9k v out ?15v 2200pf 2200pf c out2 330f 2 v out ?15v 10a c out1 10f 2 3840f lt 3840

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